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Intel® Threading Building Blocks (Intel® TBB)
Simple Mutex - Example

The following examples shows basic usage of a
Intel® Threading Building Blocks (Intel® TBB)
mutex to protect a shared variable named
count
using simple mutexes and scoped locks:

Simple Mutex Example

#include <tbb/mutex.h> int count; tbb::mutex countMutex; int IncrementCount() { int result; // Add Intel TBB mutex countMutex.lock(); // Implements ANNOTATE_LOCK_ACQUIRE() result = count++; // Save result until after unlock countMutex.unlock(); // Implements ANNOTATE_LOCK_RELEASE() return result; }
The semantics of
countMutex.lock()
and
unlock()
on countMutex correspond directly to the annotations
ANNOTATE_LOCK_ACQUIRE()
and
ANNOTATE_LOCK_RELEASE()
. However, it is generally better to use the
scoped locking
pattern.

Scoped Lock Example

With a scoped lock, you construct a temporary
scoped_lock
object that represents acquisition of a lock. Destruction of the
scoped_lock
object releases the lock on the mutex.
The following code shows the previous example rewritten using scoped locking:
#include <tbb/mutex.h> int          count; tbb::mutex   countMutex; int IncrementCount() { int result; { // Add Intel TBB scoped lock at location of ANNOTATE_LOCK annotations tbb::mutex::scoped_lock lock(countMutex); // Implements ANNOTATE_LOCK_ACQUIRE() result = count++; // Implicit ANNOTATE_LOCK_RELEASE() when leaving the scope below. } // scoped lock is automatically released here return result; }
The
scoped_lock
pattern is preferred because it releases the lock no matter how control leaves the block. The scoped lock is released when destruction of the
scoped_lock
object occurs. In particular, it releases the lock even when control leaves because an exception was thrown.
Intel TBB
also has a
tbb::atomic
template class that can be used in simple cases such as managing a shared integer variable. Check the Related Information for details.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804