User Guide

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Parallelize Data -
Intel® Threading Building Blocks (Intel® TBB)
Loops with Complex Iteration Control

Sometimes the loop control is spread across complex control flow. Using
Intel® Threading Building Blocks (Intel® TBB)
in this situation requires more features than the simple loops. Note that the task body must not access any of the auto variables defined within the annotation site, because they may have been destroyed before or while the task is running. Consider this serial code:
 extern char a[]; int previousEnd = -1; ANNOTATE_SITE_BEGIN(sitename); for (int i=0; i<=100; i++) { if (!a[i] || i==100) { ANNOTATE_TASK_BEGIN(do_something); DoSomething(previousEnd+1,i); ANNOTATE_TASK_END(); previousEnd=i; } } ANNOTATE_SITE_END();
In general, counted loops have better scalability than loops with complex iteration control, because the complex control is inherently sequential. Consider reformulating your code as a counted loop if possible.
The prior example is easily converted to parallelism by using the
task_group
feature of
Intel TBB
:
  #include <tbb/tbb.h> ... extern char a[]; int previousEnd = -1; task_group g; for (int i=0; i<=100; i++) { if (!a[i] || i==100) { g.run([=]{DoSomething(previousEnd+1,i);} previousEnd=i; } } g.wait(); // Wait until all tasks in the group finish  
Here the lambda expression uses capture by value
[=]
because it is important for it to grab the values of
i
and
previousEnd
when the expression constructs its
functor
, because afterwards the value of
previousEnd
and
i
change.
For more information on
tbb::task_group
, see the
Intel TBB
documentation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804