User Guide

Contents

Data Sharing Problems

In a serial program, the order of the operations during program execution are known. However, when code executes as multiple parallel tasks, an operation can execute before, after, or simultaneously with an operation in the other task. For example, when parallel tasks access or modify a shared memory location, data sharing problems can occur.
The
Intel® Advisor
Dependencies tool performs extensive analysis of your running serial program to help you predict data sharing problems. Use the
Dependencies Report
window and the topics introduced by this section to help you understand and decide how to fix the reported data sharing problems.
For each data sharing problem, you can either:
  • Modify the sources to fix
    incidental
    or accidental data sharing by privatizing shared data use. This type of data sharing occurs when tasks use the same memory location, but do not communicate about using that memory location. If the data written by one is not needed by the other, each task could use a private copy of the data.
  • Add lock annotations to implement synchronization for
    independent updates
    . This type of sharing occurs when multiple tasks contribute to determining the final value of a memory location.
  • Recognize that the order of the operations cannot change, and consider modifying the chosen parallel sites and their tasks. When shared data access must occur in the original sequential order, this is called
    true dependence
    .
The following sections explain how to understand and fix sharing problems.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804