User Guide

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Synchronization

You can fix independent update sharing problems by synchronizing the execution of code that uses the same memory locations. The key idea is that when two or more tasks contain groups of operations which should not execute at the same time, there must be a lock which controls the execution of all of these groups of operations. Such a group of operations is called a
transaction
, and may be anything from a read/modify/write of a single variable to a collection of related modifications to multiple data structures.
Before beginning a transaction, a task must
acquire
the lock that controls it, and when the transaction is done, the task must
release
it. If one task has already acquired a lock, then another task that tries to acquire the same lock will stop executing until the first task has released it. This guarantees that two transactions controlled by the same lock cannot execute at the same time.
Use the Advisor lock annotations
ANNOTATE_LOCK_ACQUIRE
and
ANNOTATE_LOCK_RELEASE
to describe a transaction you intend to lock. Later, you will modify the lock annotations to actual code that implements a lock using the chosen parallel framework code:
void do_something() {     static bool initialized = false;     ANNOTATE_LOCK_ACQUIRE(0);     if (!initialized) {         do_the_initialization();         initialized = true;     }     ANNOTATE_LOCK_RELEASE(0);     do_the_real_work(); }
Locks are identified by a lock address.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804