User Guide


Support for Data Parallel C++ Applications

Flow Graph Analyzer is a feature of Intel® Advisor that allows you to explore, debug, and analyze graph computation problems. Since the DPC++ runtime constructs an asynchronous task graph from submitted work, Flow Graph Analyzer allows you to visualize and interact with the asynchronous task graph, and its execution traces. The tool introduces the following features:
  • For a CPU device: Execution trace-based analytics.
  • For CPU and GPU devices: Graph-related analytics.
The data collection support for DPC++ applications is currently supported only on Linux* OS.
The code sample below illustrates a simple example of a DPC++ application that adds two vectors. The subsequent sections will use it as an example.
#include <CL/sycl.hpp> #include <iostream> #define VECTOR_SIZE 16384 using namespace cl::sycl; void vec_add(queue &q, const float A[], const float B[], float C[], const int size) { // Create the buffers buffer<float, 1> bufA(A, range<1>(VECTOR_SIZE)); buffer<float, 1> bufB(B, range<1>(VECTOR_SIZE)); buffer<float, 1> bufC(C, range<1>(VECTOR_SIZE)); q.submit([&](handler &cgh) { auto Acc = bufA.get_access<access::mode::read>(cgh); auto Bcc = bufB.get_access<access::mode::read>(cgh); auto Ccc = bufC.get_access<access::mode::write>(cgh); cgh.parallel_for<class saxpy_kernel>(range<1>(size), [=](id<1> idx) { Ccc[idx[0]] = Acc[idx[0]] + Bcc[idx[0]]; }); }); } int main(int argc, char **argv) { if (argc < 2) { std::cout << "Usage:- " << argv[0] << " [cpu, gpu]\n"; return 1; } if (argc < 2) { std::cout << "Usage:- " << argv[0] << " [cpu, gpu]\n"; return 1; } float A[VECTOR_SIZE], B[VECTOR_SIZE], C[VECTOR_SIZE]; if (std::string("cpu") == argv[1]) { cpu_selector device; queue q(device); vec_add(q, A, B, C, VECTOR_SIZE); } else if (std::string("gpu") == argv[1]) { gpu_selector device; queue q(device); vec_add(q, A, B, C, VECTOR_SIZE); } return 0; }

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804