User Guide


Examine a DPC++ Application Graph

The visualization of Data Parallels C++ (DPC++) applications is similar to data from other run-times, such as Threading Building Blocks (TBB) or OpenMP*. The graph in DPC++ represents the asynchronous task graph created from the end-user construct such as buffer accessors, command group handler, and data parallel constructs such as
The data from the sample viewed in Flow Graph Analyzer is shown above. As with other runtimes, the graph view is correlated with the execution trace views. The workflows will provide similar information for DPC++. To better visualize the overlapping tasks in the execution trace view, select the
Stacked View
attribute from the pull-down menu as shown below:
This will change the view to an icicle chart that displays everything in detail, and you can see the calls to the OpenCL™ stack.
Clicking on a task in the timeline views will highlight a node in the graph if that task belongs to the graph. If you want to highlight all the tasks that belong to a graph node, you should enable task highlighting button and select a node on the graph to see the associations.
The screenshot below shows the tasks that belong to the
are highlighted in a different color. Using the correlation features, one can debug the execution profile of the application to get a better understanding of the execution. Flow Graph Analyzer also includes features that target specific performance-related issues and the other sections go into detail for each one of these potential performance problems.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804