User Guide


Experimental Support for OpenMP* Applications

You can now trace, visualize, and analyze OpenMP* parallel regions, tasks, and task dependencies in your application with the Flow Graph Analyzer.
The Flow Graph Analyzer support for OpenMP technology is experimental and currently covers two basic scenarios:
  • OpenMP parallel regions are nested inside a Threading Building Blocks (TBB) flow graph. For this case, the Flow Graph Analyzer shows the execution of the parallel regions in the per-thread task execution timelines.
    The sample code below,
    , is an example of an OpenMP
    nested inside a TBB flow graph:
    #include "tbb/tbb.h" #include "tbb/flow_graph.h" #include<omp.h> #include <iostream> using namespace tbb; using namespace tbb::flow; int main() { graph g; const int size = 20; continue_node< continue_msg> hello( g, []( const continue_msg &) { std::cout << "Hello\n"; tbb::parallel_for(0, size, 1, [=](int k) { std::cout << k << "\n"; }); }); continue_node< continue_msg> world( g, []( const continue_msg &) std::cout << " World\n";
    #pragma omp parallel for
    for (int i=0; i<20; i++) {
    std::cout << i <<"\n";
    } ); make_edge(hello, world); hello.try_put(continue_msg()); g.wait_for_all(); return 0; }
  • OpenMP tasks that use
    clauses. In this, the Flow Graph Analyzer shows task execution in the timelines and provides experimental support that lets you see the dependency relationships between OpenMP tasks as a graph in the graph canvas.
    The sample code below,
    , is a hello-world example of OpenMP task dependencies:
    #include <omp.h> #include<iostream> int main() { #pragma omp parallel { std::string s = ""; #prgma omp single {
    #pragma omp task depend( out: i)
    { s = "hello"; printf("%s", s); }
    #pragma omp task depend( out: s )
    { s = "world"; printf("%s",s); } } } return 0; }

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804