User Guide

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Nested Parallelism in Flow Graph Analyzer

The Flow Graph Analyzer supports visualization of applications that contain multiple levels of parallelism, such as nested Threading Building Blocks (TBB) algorithms and OpenMP* parallel regions. This feature requires additional support from the parallel runtime libraries and can be used in combination with a TBB flow graph.
The sample code below is an example of nested parallelism that combines a TBB flow graph, a TBB
parallel_for
algorithm, and an OpenMP* parallel region.
#include "tbb/tbb.h" #include "tbb/flow_graph.h" #include <omp.h> #include <iostream> using namespace tbb; using namespace tbb::flow; int main() { graph g; const int size = 20; continue_node< continue_msg> hello( g, []( const continue_msg &) { std::cout << "Hello\n"; tbb::parallel_for(0, size, 1, [=](int k) { std::cout << k << "\n"; }); }); continue_node< continue_msg> world( g, []( const continue_msg &) std::cout << " World\n"; #pragma omp parallel for for (int i=0; i<20; i++) { std::cout << i <<"\n"; } } ); make_edge(hello, world); hello.try_put(continue_msg()); g.wait_for_all(); return 0; }

Tracing Nested Threading Building Blocks (TBB) Algorithms

Threading Building Blocks (TBB) 2019 enables general tracing of parallel algorithms, which is enabled by default and activated by the Flow Graph Analyzer trace collector.
As a result, Flow Graph Analyzer can display TBB library activity in nested and non-nested algorithms. Therefore, task context switches are captured and can be visualized in the Flow Graph Analyzer GUI. This work is similar to tasks in the timeline and is named according to its algorithm (for example,
parallel_for
).
This information might not be available for user-defined task groups.

Tracing Nested OpenMP* Algorithms

For detailed information on Flow Graph Analyzer support for OpenMP* technology, see Experimental Support for OpenMP* Applications.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804