User Guide

Contents

Code Region is not Marked Up

Symptoms

A code region of interest is not analyzed and has
Outside of Marked Region
message in the Why Not Offloaded column of the HTML report
.

Details

To limit the scope of collections, the
Intel® Advisor Beta
selects loops that match certain criteria and marks them up for analysis. By default, the
Intel® Advisor Beta
performs a smart region selection using the
generic
markup.
If a code region does not satisfy the markup criteria, you should see the
Outside of Marked Region
message in the Why Not Offloaded column
or the
System Module
message in the Diagnostics column in the HTML report
.

Cause

Your code region does not satisfy one or more markup rules for a specified markup mode. If you use the default generic mark-up strategy, make sure your loop of interest satisfies the following rules:
  • It is not a system module or a system function.
  • It has instruction mixes.
  • It is executed.
  • Its execution time is not less than 0.02 seconds, which is a sampling interval of the
    Intel® Advisor Beta
    . For more information about execution time limitations, see Total Time is Too Small for Reliable Modeling.

Possible Solution

If a code region does not satisfy the generic markup rules, but you want to analyze it, do one of the following:
  • You can change the markup strategy by using a
    --markup=<markup_mode>
    option with a parameter other than
    generic
    . The following parameters select only loops inside regions that are already parallel:
    • regions
      - Select loops in OpenMP*, Data Parallel C++ (DPC++), Intel® Data Analytics Acceleration Library (Intel® DAAL), Threading Building Blocks (TBB) parallel regions.
    • omp
      - Select loops only in OpenMP parallel regions.
    • dpcpp
      - Select loops only in DPC++ parallel regions.
    • daal
      - Select loops only in Intel DAAL parallel regions.
    • tbb
      - Select loops only in TBB parallel regions.
    omp
    ,
    dpcpp
    , and
    generic
    select loops in the project so you can run another collection or performance modeling without markup or loop selection options.
  • If your loops of interest are not marked up because they have no static instruction mixes or not executed, you can limit the analysis to these specific loops by using the
    --select-loops
    option with the
    analyze.py
    script. With this option, the Offload Advisor analyzes only the loops specified and ignores other code regions. For example:
    advixe-python <APM>/analyze.py <project-dir> --select-loops=[<file-name1>:<line-number1>,<file-name1>:<line-number2>,<file-name2>:<line-number3>]
    Replace
    <APM>
    with
    $APM
    on Linux* OS or
    %APM%
    on Windows* OS.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804