User Guide

Contents

cache-config

Set the cache hierarchy to collect modeling data for CPU cache behavior during Trip Counts & FLOP analysis.

Syntax

--cache-config
=
<string>
Arguments
<string>
follows this template:
[num_of_level1_caches]:[num_of_ways_level1_connected]:[level1_cache_size]:[level1_cacheline_size]/
[num_of_level2_caches]:[num_of_ways_level2_connected]:[level2_cache_size]:[level2_cacheline_size]/
[num_of_level3_caches]:[num_of_ways_level3_connected]:[level3_cache_size]:[level3_cacheline_size]
For example: 4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l
Actions Modified
collect
=tripcounts --enable-cache-simulation
collect
=roofline --enable-cache-simulation
Usage
When no specific configuration is set, the
Intel Advisor
uses system cache hierarchy for modeling.
Cache simulation modeling applies to the following
analyses
:
  • Memory Access Patterns
    analysis
    - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.
  • Trip Counts and FLOP / Roofline - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.
This option is applicable only to Trip Counts and FLOP and Roofline analyses.
  1. Run a Survey analysis.
  2. Run a Trip Counts & FLOP analysis. Model cache behavior for the specified configuration.
$ advixe-cl –-collect=survey –-project-dir=./advi -- myApplication
$ advixe-cl --collect=tripcounts --flop –-enable-cache-simulation --cache-config=4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l –-project-dir=./advi -- myApplication
Run Roofline analysis for all memory levels (Memory-Level Roofline) for the specified cache configuration.
$ advixe-cl –-collect=roofline --enable-cache-simulation --cache-config=4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l –-project-dir=./advi -- myApplication

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804