User Guide



Set the cache associativity for modeling CPU cache behavior during Memory Access Patterns analysis.


is the number of cache locations where one memory entry can be placed: 1 | 2 | 4 | 8 | 16
Actions Modified
=map --enable cache-simulation
stands for a direct mapped cache, where a memory entry can occupy only one cache line.
Cache simulation modeling applies to the following
  • Memory Access Patterns
    - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.
  • Trip Counts and FLOP / Roofline - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.
This option is applicable only to Memory Access Patterns analysis.
Run a Memory Access Patterns analysis. Model four-way associative cache with default cache line and cache set size.
$ advixe-cl --collect=map --enable-cache-simulation --cachesim-associativity=4 --cachesim-mode=utilization --project-dir=./myAdvisorProj -- ./myApp

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804