User Guide

Contents

cachesim-mode

Set the focus for modeling CPU cache behavior during Memory Access Patterns analysis.

Syntax

--cachesim-mode
=
<string>
Arguments
<string>
is one of the following:
Argument
Description
cache-misses
Model cache misses only.
footprint
Model cache misses and memory footprint of a loop. Calculation: Cache line size x Number of unique cache lines accessed during simulation.
utilization
Model cache misses and cache lines utilization.
Default
utilization
Actions Modified
collect
=map --enable cache-simulation
Usage
For memory footprint simulation, the
Intel Advisor
tracks only a subset of accesses and cache lines, and scales it up to the total size of cache to calculate the final footprint value.
Cache simulation modeling applies to the following
analyses
:
  • Memory Access Patterns
    analysis
    - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.
  • Trip Counts and FLOP / Roofline - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.
This option is applicable only to Memory Access Patterns analysis.
Usage can increase analysis overhead.
Run a Memory Access Patterns analysis. Model cache misses for a default cache configuration.
$ advixe-cl collect=map --enable-cache-simulation --cachesim-mode=cache-misses --project-dir=./myAdvisorProj -- ./myApp
Run a Memory Access Patterns analysis. Model cache miss and memory footprint data for 1024-byte cache set size, default cache associativity and cache line size.
$ advixe-cl collect=map --enable-cache-simulation --cachesim-sets=1024 --cachesim-mode=footprint --project-dir=./myAdvisorProj -- ./myApp

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804