User Guide

Contents

Data Reference

This reference section describes the contents of data columns in
Survey
and
Refinement Reports
.
A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | XYZ

Access Pattern

Description
: Summary of access types.

Access Type

Description
: Memory access type: Read, Write, Read/Write
Collected
 during Memory Access Patterns Analysis and
found
 in
Memory Access Patterns Report
.

Address Range

Description
: Instruction address range in memory.
Interpretation
: A wide range indicates one or more of the following:
  • The application uses too much memory.
  • Memory usage is not optimal.

Average

Description
: Loop trip count average.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

B

Cache Line Utilization

Description
: Simulated cache line utilization for data transfer operations.

Cache Misses

Description
: Number of memory load operations served by memory subsystem higher than cache. Calculated for the first instance of the loop (assuming
cold
CPU cache). Value is a result of virtual cache modeling, which might not match exact counter reported by hardware for this analysis run.

Call Count

Description
: Number of times loop/function was invoked.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.
Interpretation
: A high number means there is an outer loop in the selected loop call chain with high trip count values. If the loop has a low trip count value, the outer loop could be a better candidate for parallelization (threading/vectorization).

Compiler Estimated Gain

Description
: Theoretical compiler estimate of relative loop performance speedup achieved or achievable due to vectorization.
Comparison with similar metrics
:
Gain Estimate
is
Intel Advisor
-calculated estimate of relative loop performance speedup achieved due to vectorization.

Data Types

Description
: Data types provided by binary static analysis.
Interpretation
: Bold indicates primary data type used for vectorization.

Description

Description
: Code location classification.
Collected
 during Dependencies Analysis and
found
 in Dependencies Report.

Dirty Evictions

Description
: Number of evicted cache lines with a modified state introducing upstream memory traffic to a higher memory subsystem.

Efficiency

Description
:
Intel Advisor
-calculated performance estimated gain compared to maximum achievable gain from vectorization.
Interpretation
: Normally means how effectively vectorization was applied, compared to maximum possible gain (higher is better).
Calculation/Aggregation
:
(Estimated gain/Vector length) * 100%
Interpretation
: Hover mouse over data cell for more information.

Elapsed Time

Description
: Elapsed (wall-clock) application time.
Collected
 during ,  and
found
 in Filters banner.

First Instance Site Footprint

Description
: For each memory access instruction for the first instance of a loop, the
Intel Advisor
:
  • Tracks the minimum and maximum access addresses.
  • Displays the maximum range in this metric.
Comparison with similar metrics
: This metric is more reliable than the
Maximum Per-Instruction Address Range
metric.
Max. Per-Instruction Addr. Range
First Instance Site Footprint
Simulated Memory Footprint
Number of threads analyzed for loop/site
1
1
1
Number of loop instances analyzed
All instances, but with some memory access instruction filtering
1
Depends on loop call count limit:
  • GUI:
    Project Properties
    Analysis Target
    Memory Access Patterns Analysis
    Advanced
    Loop call count limit
  • CLI action option: -loop-call-count limit
Awareness of overlap between address ranges accessed in loop
No
Yes
Yes
Suitability for code with random memory access
No
No
Yes

Function

Description
: Function name.
Collected
 during Dependencies Analysis 
and found in
 Dependencies Report.

Function Call Sites and Loops

Description
: Information about parent function, source file, and line where site/loop begins in Loop Information Pane (Survey Report), and top-down call tree of target functions and loops in Loop Information Pane (Survey Report)
Interpretation
:
  • - Scalar function.
  • - Vectorized function.
  • - Scalar loop. Vectorization might be possible.
  • - Vectorized loop. Optimization might be possible.
  • - Scalar inner loop within vectorized outer loop. Optimization might be possible.

Gain Estimate

Description
:
Intel Advisor
-calculated estimate of relative loop performance speedup achieved due to vectorization.
Comparison with similar metrics
:
Compiler Estimated Gain
is the theoretical compiler estimate of relative loop performance speedup achieved or achievable due to vectorization.

H

Instruction Address

Description
: Instruction address in memory.
Collected
 during Dependencies Analysis and
found
 in Dependencies Report.

Instruction Sets

Description
: Instruction Set Architecture (ISA) usage for individual instructions.

Iteration Duration

Description
: Average loop iteration time.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

J

K

Loop Instance Total Time

Description
: Average loop instance total time.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

Loop-Carried Dependencies

Description
: Dependencies summary across iterations
Possible values
:
  • RAW
    (Read after Write) - Flow dependency
  • WAR
    (Write after Read) - Anti dependency
  • WAW
    (Write after Write) - Output dependency

Max

Description
: Loop trip count maximum.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

Max Site Footprint

Description
: Maximum distance (among all instances of the loop) between the minimum and maximum memory address values.

Maximum Per-Instruction Address Range

Description
: For most memory access instructions for all instances of a loop, the
Intel Advisor
:
  • Tracks the minimum and maximum access addresses.
  • Displays the maximum range in this metric.
The value may be imprecise because the
Intel Advisor
filters some memory access instructions while analyzing all instances of a loop. Unreliable values are displayed in gray.
Collected
during Memory Access Patterns Analysis and
found
in Loop Information Pane (Refinement Reports) and Memory Access Patterns Report.
Comparison with similar metrics
: This metric is less reliable than the
First Instance Site Footprint
metric.
Max. Per-Instruction Addr. Range
First Instance Site Footprint
Simulated Memory Footprint
Number of threads analyzed for loop/site
1
1
1
Number of loop instances analyzed
All instances, but with some memory access instruction filtering
1
Depends on loop call count limit:
  • GUI:
    Project Properties
    Analysis Target
    Memory Access Patterns Analysis
    Advanced
    Loop call count limit
  • CLI action option: -loop-call-count limit
Awareness of overlap between address ranges accessed in loop
No
Yes
Yes
Suitability for code with random memory access
No
No
Yes

Memory Access Footprint

Description
: Maximum distance (among all instances of the loop) between minimum and maximum memory address values, accessed by the instructions, generated from the current source line.

Memory Loads

Description
: Number of memory load operations in first instance of the loop.

Memory Stores

Description
: Number of memory store operations in first instance of the loop.

Memory, GB

Description
: Number of data transfers, in GB, between the CPU and memory subsystem.
This is a core metric that is the basis of the arithmetic intensity (AI) calculation.

Min

Description
: Loop trip count minimum.
Prerequisites for collection/display
: Enabled
Trip Counts
on Workflow tab
or enabled
Collect information about Loop Trip Counts
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

Module/Modules

Description
: Executable or library name.

Multi-Pumping Factor

Description
: The number of times the compiler applied a pumping optimization to extend vector length.

Nested Function

Description
: Name of the function (invoked from the site) where the stride diagnostic was detected.
Collected
during Memory Access Patterns Analysis and
found
in Memory Access Patterns Report.

Optimization Details

Description
: Compiler optimization details.

Performance Issues

Description
: Performance issues found.
Interpretation
: Click to display confidence level about issue root cause and recommended fixes.

Problem Severity

Description
: Seriousness of a detected problem.
Possible values
:
  • - Error.
  • - Warning.
  • - Informational.

Q

RFO Cache Misses

Description
: Number of cache lines loaded to cache due to a modification request (Request for Ownership).

Self AI

Description
: Ratio of
Self GFLOPS
to self L1 transferred bytes.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Floating-Point Operation Columns
    for column setting.

Self Elapsed Time

Description
:
Self Time
-based wall time from beginning to end of loop/function execution, excluding time for callees.
Comparison with similar metrics
:
Total Elapsed Time
is
Total Time
-based wall time from beginning to end of loop/function execution, including time for callees.
Interpretation
: Same as
Self Time
for single-threaded applications

Self GFLOP

Description
: Giga floating-point operations, excluding GFLOP for callees.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Floating-Point Operation Columns
    for column setting.

Self GFLOPS

Description
: Ratio of
Self GLOP
to
Self Elapsed Time
.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Floating-Point Operation Columns
    for column setting.

Self Giga OP

Description
: Giga floating-point operations plus giga integer operations, excluding giga floating-point and integer operations for callees.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Sum of Integer and Floating-Point Operation Columns
    for column setting.

Self Giga OPS

Description
: Ratio of
Self GFLOP
plus
Self GINTOP
to
Self Elapsed Time
.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Sum of Integer and Floating-Point Operation Columns
    for column setting.

Self GINTOP

Description
: Giga integer operations, excluding giga integer operations for callees.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Integer Operation Columns
    for column setting.

Self GINTOPS

Description
: Ratio of
Self GINTOP
to
Self Elapsed Time
.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Integer Operation Columns
    for column setting.

Self INT AI

Description
: Ratio of
Self GINTOPS
to self L1 transferred bytes.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Integer Operation Columns
    for column setting.

Self Memory (GB)

Description
: Data transfers between CPU and memory subsystem (total traffic, including caches and DRAM) in gigabytes, excluding transfers for callees.
Prerequisites for collection/display
: Enabled
FLOP
on Workflow tab
or enabled
Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.

Self Memory (GB/s)

Description
: Data transfers between CPU and memory subsystem (total traffic, including caches and DRAM) in gigabytes per second, excluding transfers for callees.
Prerequisites for collection/display
: Enabled
FLOP
on Workflow tab
or enabled
Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
on
Trip Counts and FLOP Analysis
tab of Project Properties Dialog Box.
Calculation/Aggregation
:

Self Overall AI

Description
: Ratio of
Self GFLOPS
plus
Self GINTOPS
to self L1 transferred bytes.
Prerequisites for collection/display
:
  • Enabled
    FLOP
    on Workflow tab
    or enabled
    Collect information about FLOP, L1 memory traffic, and AVX-512 mask usage
    on
    Trip Counts and FLOP Analysis
    tab of Project Properties Dialog Box.
  • Selected
    Show Sum of Integer and Floating-Point Operation Columns
    for column setting.

Self Time

Description
: Time actively executing a function/loop, excluding time for callees.
Comparison with similar metrics
:
Total Time
is time actively executing a function/loop, including time for callees.

Simulated Memory Footprint

Description
: The summarized and overlap-aware memory footprint across all instances of a loop.
Prerequisites for collection/display
:
  • Enable
    Enable CPU cache simulation
    .
  • In the
    Cache simulation mode
    drop-down list, choose
    Model cache misses and loop footprint
    .
  • Tweak other
    Enable CPU cache simulation
    parameters as necessary.
CLI example:
advixe-cl -collect map -mark-up-list=1,2,7,17,26 -enable-cache-simulation -cachesim-mode=footprint -project-dir C:\my_advisor_project -- my_application.exe
Comparison with similar metrics
:
Max. Per-Instruction Addr. Range
First Instance Site Footprint
Simulated Memory Footprint
Number of threads analyzed for loop/site
1
1
1
Number of loop instances analyzed
All instances, but with some memory access instruction filtering
1
Depends on loop call count limit:
  • GUI:
    Project Properties
    Analysis Target
    Memory Access Patterns Analysis
    Advanced
    Loop call count limit
  • CLI action option: -loop-call-count limit
Awareness of overlap between address ranges accessed in loop
No
Yes
Yes
Suitability for code with random memory access
No
No
Yes
Calculation/Aggregation
:
Number of unique cache lines accessed during cache simulation * Cache line size
.
For performance reasons, not all accesses and cache lines are simulated. Instead the
Intel Advisor
tracks a subset and then scales up to the whole cache size to determine the final footprint value.

Site Location

Description
: Information about parent function, source file, and line where site/loop begins.

Site Name

Description
: Site name if using source annotations; sequence ID if marking loops for deeper analysis in
Survey Report
.
Collected
during Dependencies Analysis and Memory Access Patterns Analysis, and
found
in Loop Information Pane (Refinement Reports), Dependencies Report, and Memory Access Patterns Report.

Source/Source Location/Sources

Description
: Source file name(s) and line number(s).

State

Description
: State of most severe problem in problem set.
Collected
during Dependencies Analysis and
found
in Dependencies Report.
Possible values
:
  • Regression
    ] - Not investigated. Set by the
    Intel Advisor
    .
    Issue requires more investigation because it was marked as
    Fixed
    in baseline result but still appears.
  • New
    ] - Not investigated. Set by the
    Intel Advisor
    or user.
    Issue did not appear in the baseline result, or there is no older result from which the
    Intel Advisor
    can propagate state information.
  • Not Fixed
    ] - Not investigated. Set by user.
    Issue appeared in the baseline result and still requires investigation.
  • Confirmed
    ] - Investigated. Set by user.
    Issue requires fixing but has not yet been fixed.
  • Fixed
    ] - Investigated. Set by user.
    Issue requires fixing and has been fixed.
  • Not a problem
    ] - Investigated. Set by user.
    Issue does not require fixing.
  • Deferred
    ] - Investigated. Set by user.
    You are postponing further investigation on an issue that may or may not require fixing.

Stride

Description
: Distance, in elements, between memory accesses in two consequent iterations.
Collected
during Memory Access Patterns Analysis and found in Memory Access Patterns Report.

Strides Distribution

Description
: Stride ratio in following format: Unit%/Constant%/Variable%

Total Elapsed Time

Description
:
Total Time
-based wall time from beginning to end of loop/function execution, including time for callees
Comparison with similar metrics
:
Self Elapsed Time
is
Self Time
-based wall time from beginning to end of loop/function execution, excluding time for callees.
Interpretation
: Same as
Total Time
for single-threaded applications.

Total Time

Description
: Time actively executing a function/loop, including time for callees.
Comparison with similar metrics
:
Self Time
is time actiely executing a function/loop, not including time for callees.

Traits

Description
: Scalar and vectorization characteristics that may impact performance.
Possible values
:
Trait
Detected ASM Instructions
Divisions
*DIV*
Square Roots
*SQRT*
Type Conversions
*CVT*
NT-stores
*MOVNT*
Gathers
*GATHER*
Scatters
*SCATTER*
Shuffles
*SHUF*
Permutes
*PERM*
Blends
*BLEND*
Packs
*PACK*
Unpacks
*UNPCK*
Inserts
*INSERT*
Extracts
*EXTRACT*
Masked Stores
*MASKMOV*
Shifts
*PROR*, *PROL*, *PSLL*, *PSRA*, *PSRL*
FMA
*FMADD*, *FMSUB*, *FNMADD*, *FNMSUB*
Mask Manipulations
*KADD*, *KTEST*, *KAND*, *KOR*, *KXOR*, *KXNOR*, *KNOT*, *KUNPCK*, *KMOV*, *KSHIFT*
Conflict Detections
*VPCONFLICT*
Exponent extractions
*VGETEXP*
Mantissa extractions
*VGETMANT*
Expands
*EXPAND*
Compresses
*COMPRESS*
VNNI
*VNNI*

Transformations

Description
: Loop transformations applied by compiler.

Type

Possible Survey Report values
:
  • Peeled/Remainder
    - For loops that have child loops. Appears only when scalar peeled loop and/or remainder loop executed.
  • Threaded
    - For loops that have child loops. Appears when some parallel framework (OpenMP* or automatically by Intel compiler) is used in the loop.
  • Vectorized (<loop part(s)>)
    - For vectorized parent and child loops. Appears when a parent loop has
    any
    of the following parts executed: peeled, body, remainder. Also appears for child loops that have
    one
    of the following parts executed: peeled, body, remainder.
  • Peeled
    - For small, (usually) compiler-generated loops created to align the memory accesses inside the loop body and maximize its efficiency.
  • Body
    - For vectorized loops (compiler-generated from a source loop). Most loop iterations should execute in body, as body normally processes more data than peeled or remainder loops. Vector length in the body is usually larger than in peeled and/or remainder loops, which means body is the most efficient place for performance.
  • Remainder
    - For (usually) compiler-generated loops created to clean up any remaining iterations that do not fit within the scope of the loop body.
  • [Not Executed]
    - Mark that appears next to any other loop metric when a loop was not executed.
  • Scalar
    - Appears when non-vectorized loops executed.
  • Completely Unrolled
    - Appears when the loop body was copied several times (equal to trip counts value) by the compiler.
  • Inside vectorized
    - Appears when the inner loop was vectorized in addition to the outer loop.
  • Inlined Function
    - Appears when the function body was inlined into the loop/function body.
  • Vector Function
    - Appears when a SIMD-enabled version of the function executed. (See Intel compiler documentation for details).
  • Function
    - Appears when a scalar version of the function executed.
Possible Memory Access Patterns Report values
:
  •  
    Uniform stride 0
    - Instruction accesses the same memory from iteration to iteration.
    Represents the ideal situation and does not require any improvements.
  •  
    Unit stride (stride 1)
    - Instruction accesses memory that consistently changes by one element from iteration to iteration.
    Represents the ideal situation and does not require any improvements.
  •  
    Constant stride (stride N)
    - Instruction accesses memory that consistently changes by N elements (N>1) from iteration to iteration.
    Code uses more memory than is ideal and requires more cache lines. Consider studying recommendations on AOS/SOA optimization.
  •  
    Irregular stride
    - Instruction accesses memory addresses that change by an unpredictable number of elements from iteration to iteration.
    Might limit vectorization or even make vectorization impossible.
  •  
    Gather (irregular) stride
    - Detected for v(p)gather* instructions on AVX2 Instruction Set Architecture (ISA).
    The compiler vectorized code with an irregular memory access pattern. Consider improving the code to use a more constant memory access pattern.
Possible Dependencies Report values
- See Problem and Message Types.

Unroll Factor

Description
: Loop unroll factor applied by the compiler.

Variable References

Description
: Name of the variable for which the dependency or memory access stride is detected.
Collected
during Dependencies Analysis and Memory Access Patterns Analysis, and
found
in Dependencies Report and Memory Access Patterns Report.

Vector ISA

Description
: The highest vector Instruction Set Architecture used for individual instructions.
Comparison with similar metrics
: An ISA higher than the ISA of your current hardware appears when you add corresponding codepaths with
x
,
Qx
/
ax
,
Qax
compiler options. To see the ISA of non-executed codepaths, enable the
Analyze non-executed codepaths
option in
Project Properties
.

Vector Widths

Description
: Vector register width in bits.
Possible values
: Combination of values, including 32, 64, 128, 256, 512, delimited by a slash or semi-colon (/ or ;).

Vectorization Details

Description
: Compiler notes on vectorization.

VL (Vector Length)

Description
: The number of elements processed in a single iteration of vector loops, or the number of elements processed in individual vector instructions.
Calculation/Aggregation
: Estimated by binary static analysis or the Intel compiler.

Why No Vectorization?

Description
: The reason the compiler did not vectorize the loop.
Interpretation
: Click to display the issue root cause and recommended fixes.

X, Y, Z

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804