User Guide

  • 2020
  • 06/18/2020
  • Public Content
Contents

Inconsistent Lock Use

Occurs when a task execution accesses a memory location more than once, under the control of different locks.
One of the following has occurred:
Problem type: Inconsistent lock use
Problem type: Inconsistent lock use
Problem type: Inconsistent lock use
ID
Code Location
Description
1
Allocation site
If present, represents the location and associated call stack when the memory was allocated.
2
Parallel site
If present, represents the location and associated call stack of the parallel site containing the Inconsistent Lock Use problem.
3
Read
Represents the location and associated call stack of the first access if it is a memory read.
4
Write
Represents the location and associated call stack of the second access if it is a memory write.
5
Read
Represents the location and associated call stack of the second access if it is a memory read.
6
Write
Represents the location and associated call stack of the first access if it is a memory write.
// Parallel site ANNOTATE_TASK_BEGIN(task); for (int i = 0; i < N; i++) { ANNOTATE_LOCK_ACQUIRE(1); a[i][j0]++; // Read and/or Write ANNOTATE_LOCK_RELEASE(1); } for (int j = 0; i < N; i++) { ANNOTATE_LOCK_ACQUIRE(2); a[i0][j]++; // Read and/or Write ANNOTATE_LOCK_RELEASE(2); } ANNOTATE_TASK_END();
In this example,
a[i0][j0]
is accessed under lock 1 in the first loop and under lock 2 in the second loop. It is likely that an access in another task will not have the right combination of locks to avoid conflicting with both these accesses.
Possible Correction Strategies
Lock all accesses to the same memory location with the same lock.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804