User Guide

Contents

Memory Reuse, Child Task

Occurs when two tasks write to a shared memory location, where a parent task overwrites a variable with a new value that was read by a previously executed child task. A child task is a task nested inside another task.
Problem type: Memory reuse
ID
Code Location
Description
1
Allocation site
If present, and if the memory involved is heap memory, represents the location and associated call stack when the memory was allocated.
2
Parallel site
If present, represents the location and associated call stack of the parallel site containing the Memory Reuse, Child Task problem.
3
Read
Represents the instruction and associated call stack of the first access if it is a memory read.
4
Write
Represents the instruction and associated call stack of the second access if it is a memory write.
int global; void main() {     ANNOTATE_SITE_BEGIN(reuse_site); // Begin parallel site         ANNOTATE_TASK_BEGIN(task111);             assert(global == 111); // Read         ANNOTATE_TASK_END();         global = 222; // Write     ANNOTATE_SITE_END(); }
In this example, a parent task is writing to a shared variable after a task that reads that same variable.
Some Possible Correction Strategies
Create a private copy of the variable before executing the child task. Use the private copy in the child task.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804