User Guide

  • 2020
  • 06/18/2020
  • Public Content
Contents

Memory Reuse

Occurs when two tasks write to a shared memory location. That is, a task writes to a variable with a new value but does not read the same value generated by a prior task.
One of the following has occurred:
Problem type: Memory reuse
Problem type: Memory reuse
ID
Code Location
Description
1
Allocation site
If present, and if the memory involved is heap memory, represents the location and associated call stack when the memory was allocated.
2
Parallel site
If present, represents the location and associated call stack of the parallel site containing the Memory Reuse problem.
3
Read
Represents the instruction and associated call stack of the first access if it is a memory read.
4
Write
Represents the instruction and associated call stack of the second access if it is a memory write.
5
Write
Represents the instruction and associated call stack of the first access if it is a memory write.
int global; void main() {     ANNOTATE_SITE_BEGIN(reuse_site); // Begin parallel site         ANNOTATE_TASK_BEGIN(task111);             global = 111; // Read and/or Write             assert(global == 111);         ANNOTATE_TASK_END();         ANNOTATE_TASK_BEGIN(task222);             global = 222; // Write             assert(global == 222);         ANNOTATE_TASK_END();     ANNOTATE_SITE_END(); }
In this example, two tasks use the same
global
variable. Each task does not read or communicate the value produced by the other task.
Some Possible Correction Strategies
Change the tasks to have their own private variables rather than sharing a variable.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804