Developer Guide and Reference


qopt-streaming-stores, Qopt-streaming-stores

Enables generation of streaming stores for optimization.


Linux and macOS:
Specifies whether streaming stores are generated. Possible values are:
Enables generation of streaming stores for optimization. The compiler optimizes under the assumption that the application is memory bound.
When this option setting is specified, it is your responsibility to also insert any fences as required to ensure correct memory ordering within a thread or across threads. One typical way to do this is to insert a _mm_sfence() intrinsic call just after the loops (such as the initialization loop) where the compiler may insert streaming store instructions.
Disables generation of streaming stores for optimization. Normal stores are performed.
Lets the compiler decide which instructions to use.
The compiler decides whether to use streaming stores or normal stores.
This option enables generation of streaming stores for optimization. This method stores data with instructions that use a non-temporal buffer, which minimizes memory hierarchy pollution.
This option may be useful for applications that can benefit from streaming stores.
Alternate Options
The following example shows a way to insert fences when specifying
void simple1(double * restrict a, double * restrict b, double * restrict c, double *d, int n) { int i, j; #pragma omp parallel for for (j=0; j<n; j++) { a[j] = 1.0; b[j] = 2.0; c[j] = 0.0; } _mm_sfence(); // OR _mm_mfence(); #pragma omp parallel for for (i=0; i<n; i++) a[i] = a[i] + c[i]*b[i]; }

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804