Developer Guide and Reference

Contents

qopt-zmm-usage, Qopt-zmm-usage

Defines a level of zmm registers usage.

Syntax

Linux and macOS:
-qopt-zmm-usage
=
keyword
Windows:
/Qopt-zmm-usage
:
keyword
Arguments
keyword
Specifies the level of zmm registers usage. Possible values are:
low
Tells the compiler that the compiled program is unlikely to benefit from zmm registers usage. It specifies that the compiler should avoid using zmm registers unless it can prove the gain from their usage.
high
Tells the compiler to generate zmm code without restrictions.
Default
varies
The default is low when you specify [Q]xCORE-AVX512.
The default is high when you specify [Q]xCOMMON-AVX512.
Description
This option may provide better code optimization for Intel® processors that are on the Intel® microarchitecture formerly code-named Skylake.
This option defines a level of zmm registers usage. The
low
setting causes the compiler to generate code with zmm registers very carefully, only when the gain from their usage is proven. The
high
setting causes the compiler to use much less restrictive heuristics for zmm code generation.
It is not always easy to predict whether the
high
or the
low
setting will yield better performance. Programs that enjoy high performance gains from the use of xmm or ymm registers may expect performance improvement by moving to use zmm registers. However, some programs that use zmm registers may not gain as much or may even lose performance. We recommend that you try both option values to measure the performance of your programs.
This option is ignored if you do not specify an option that enables Intel® AVX-512, such as
[Q]xCORE-AVX512
or option
[Q]xCOMMON-AVX512
.
This option has no effect on loops that use
pragma omp simd simdlen(n)
or on functions that are generated by vector specifications specific to CORE-AVX512.
Alternate Options
None

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804