Developer Guide and Reference

Contents

fp-trap-all, Qfp-trap-all

Sets the floating-point trapping mode for all routines.

Syntax

Linux:
-fp-trap-all
=
mode
[
,
mode
,...
]
macOS:
-fp-trap-all
=
mode
[
,
mode
,...
]
Windows:
/Qfp-trap-all
:
mode
[
,
mode
,...
]
Arguments
mode
Is the floating-point trapping mode. If you specify more than one mode value, the list is processed sequentially from left to right. Possible values are:
[no]divzero
Enables or disables the IEEE trap for division by zero.
[no]inexact
Enables or disables the IEEE trap for inexact result.
[no]invalid
Enables or disables the IEEE trap for invalid operation.
[no]overflow
Enables or disables the IEEE trap for overflow.
[no]underflow
Enables or disables the IEEE trap for underflow.
[no]denormal
Enables or disables the trap for denormal.
all
Enables all of the above traps.
none
Disables all of the above traps.
common
Sets the most commonly used IEEE traps: division by zero, invalid operation, and overflow.
Default
-fp-trap-all=none
or
/Qfp-trap-all:none
No traps are enabled for all routines.
Description
This option sets the floating-point trapping mode for the main routine. It does not set a handler for floating-point exceptions.
The
[no]
form of a
mode
value is only used to modify the meaning of
mode
values
all
and
common
, and can only be used with one of those values. The
[no]
form of the option by itself does not explicitly cause a particular trap to be disabled.
Use
mode
value
inexact
with caution. This results in the trap being enabled whenever a floating-point value cannot be represented exactly, which can cause unexpected results.
If
mode
value
underflow
is specified, the compiler ignores the FTZ (flush-to-zero) bit state of Intel® Streaming SIMD Extensions (Intel® SSE) floating-point units.
When a DAZ (denormals are zero) bit is set in an Intel® SSE floating-point unit control word, a denormal operand exception is never generated.
To set the floating-point trapping mode for the main routine only, specify the
[Q]fp-trap
option.
The negative form of the
[Q]ftz
option can be used to set or reset the FTZ and the DAZ hardware flags.
Alternate Options
None

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804