Developer Guide and Reference

Contents

inline-max-size, Qinline-max-size

Specifies the lower limit for the size of what the inliner considers to be a large routine.

Syntax

Linux and macOS:
-inline-max-size
=
n
-no-inline-max-size
Windows:
/Qinline-max-size
=
n
/Qinline-max-size-
Arguments
n
Is a positive integer that specifies the minimum size of what the inliner considers to be a large routine.
Default
-inline-max-size
or
/Qinline-max-size
The compiler sets the maximum size (
n
) dynamically, based on the platform.
Description
This option specifies the lower limit for the size of what the inliner considers to be a large routine (
a function
). The inliner classifies routines as small, medium, or large. This option specifies the boundary between what the inliner considers to be medium and large-size routines.
The inliner prefers to inline small routines. It has a preference against inlining large routines. So, any large routine is highly unlikely to be inlined.
If you specify
-no-inline-max-size
(Linux* and
macOS*
) or
/Qinline-max-size-
(Windows*), there are no large routines. Every routine is either a small or medium routine.
To see compiler values for important inlining limits, specify option
[q or Q]opt-report
.
When you use this option to increase the default limit, the compiler may do so much additional inlining that it runs out of memory and terminates with an "out of memory" message.
Alternate Options
None

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804