Developer Guide and Reference

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_allow_cpu_features

Tells the compiler that the code region may be targeted for processors with the specified features. The compiler may then generate optimized code for the specified features.

Syntax

extern void _allow_cpu_features(unsigned __int64);
Arguments
unsigned __int64
an unsigned __int64 bitset representing one or more cpuid features:
_FEATURE_GENERIC_IA32
_FEATURE_FPU
_FEATURE_CMOV
_FEATURE_MMX
_FEATURE_FXSAVE
_FEATURE_SSE
_FEATURE_SSE2
_FEATURE_SSE3
_FEATURE_SSSE3
_FEATURE_SSE4_1
_FEATURE_SSE4_2
_FEATURE_MOVBE
_FEATURE_POPCNT
_FEATURE_PCLMULQDQ
_FEATURE_AES
_FEATURE_F16C
_FEATURE_AVX
_FEATURE_RDRND
_FEATURE_FMA
_FEATURE_BMI
_FEATURE_LZCNT
_FEATURE_HLE
_FEATURE_RTM
_FEATURE_AVX2
_FEATURE_ADX
_FEATURE_RDSEED
_FEATURE_AVX512DQ
_FEATURE_AVX512F
_FEATURE_AVX512ER
_FEATURE_AVX512PF
_FEATURE_AVX512CD
_FEATURE_AVX512BW
_FEATURE_AVX512VL
_FEATURE_SHA
_FEATURE_MPX
_FEATURE_AVX512IFMA52
_FEATURE_AVX512VBMI
_FEATURE_AVX512_4FMAPS
_FEATURE_AVX512_4VNNIW
Description
Use this intrinsic function to use the specified processor feature at a code block level. The function only affects the scope of the code following the function call. Ensure that the code block will run only on processors with the specified features. If the code runs on a processor without the specified feature, the program may fail with an illegal instruction exception.
The function accepts a single argument that is a bitmask. In cases where one ISA depends on another, the higher ISA typically implies the lower. For example, the following arguments produce the same assembly code:
  • _FEATURE_SSE2|_FEATURE_AVX|_FEATURE_AVX512F
  • _FEATURE_AVX512F
The argument can only add features to those specified by the
[Q]x
or
-m
(Linux* and
macOS*
) or
/arch
(Windows*) options, it cannot remove features.
This function does not itself cause the compiler to generate multiple code paths. To do that, you need to use
_may_i_use_cpu_feature()
.
See the Release Notes for the latest information about this function.
To use specified processor features at a function level, use the
cpu_dispatch
or the
cpu_specific
attribute or the
optimization_parameter
pragma.
To use specified processor features at the file level, use the
[Q]x
compiler option.
The following example demonstrates how to use this intrinsic function to allow the compiler to generate the necessary code to use the Advanced Vector Extensions (AVX) and Streaming SIMD Extensions 2 (SSE2) features in the processor.
#include <string.h> #include <immintrin.h> #define MAXIMGS 20 #define MAXNAME 512 typedef struct { int x; /* image X axis size */ int y; /* image Y axis size */ int bpp; /* image bits */ char name[MAXNAME]; /* image full filename */ unsigned char * data; /* pointer to raw byte image data */ } rawimage; extern rawimage * imagelist[MAXIMGS]; extern int numimages; rawimage* CreateImage(char * filename) { rawimage* newimage = NULL; int i, len, intable; intable=0; if (numimages!=0) { _allow_cpu_features(_FEATURE_SSE2 | _FEATURE_AVX); for (i=0; i<numimages; i++) { if (!strcmp(filename, imagelist[i]->name)) { newimage=imagelist[i]; intable=1; } } } if (!intable) { newimage=(rawimage *)malloc(sizeof(rawimage)); if (newimage != NULL) { strcpy(newimage->name, filename); imagelist[numimages]=newimage; /* add new one to the table */ numimages++; /* increment the number of images */ } } return newimage; }
Returns
Returns nothing.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804