Developer Guide and Reference

Contents

_mm256_hadd_epi16/32

Horizontally adds adjacent signed packed 16/32-bit integer data elements of two vectors. The corresponding Intel® AVX2 instruction is
VPHADDW
or
VPHADDD
.

Syntax

extern __m256i _mm256_hadd_epi16(__m256i s1, __m256i s2);
extern __m256i _mm256_hadd_epi32(__m256i s1, __m256i s2);
Arguments
s1
integer source vector used for the operation
s2
integer source vector used for the operation
Description
Adds two adjacent 16- or 32-bit signed integers horizontally from source vectors,
s1
and
s2
and packs the 16 or 32-bit signed results to the destination vector.
Horizontal addition of two adjacent data elements of the low 16- or 32-bytes of the first and second source vectors are packed into the low 16- or 32-bytes of the destination vector. Horizontal addition of two adjacent data elements of the high 16- or 32-bytes of the first and second source vectors are packed into the high 16- or 32-bytes of the destination vector.
Returns
Result of the horizontal addition operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804