Developer Guide and Reference

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_mm256_sra_epi16/32

Arithmetic shift of word/doubleword elements to right according to specified number. The corresponding Intel® AVX2 instruction is
VPSRAW
, or
VPSRAD
.

Syntax

extern __m256i _mm256_sra_epi16(__m256i s1, __m128i count);
extern __m256i _mm256_sra_epi32(__m256i s1, __m128i count);
Arguments
s1
integer source vector used for the operation
count
128-bit memory location used for the operation
Description
Performs an arithmetic shift of bits in the individual data elements (16-bit word or 32-bit doubleword) in the first source vector
s1
to the right by the number of bits specified in
count
. The empty high-order bits are filled with the initial value of the sign bit. If the value specified by
count
is greater than 15/31/63 (depending on the intrinsic being used), the destination vector is filled with the initial value of the sign bit.
The
count
argument is a 128-bit memory location. Note that only the first 64-bits of a 128-bit count operand are checked to compute the count.
Returns
Result of the right-shift operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804