Developer Guide and Reference

Contents

_mm256_cmpgt_epi8/16/32/64

Compares packed bytes/words/doublewords/quadwords of two source vectors. The corresponding Intel® AVX2 instruction is
VPCMPGTB
,
VPCMPGTW
,
VPCMPGTD
, or
VPCMPGTQ
.

Syntax

extern __m256i _mm256_cmpgt_epi8(__m256i s1, __m256i s2);
extern __m256i _mm256_cmpgt_epi16(__m256i s1, __m256i s2);
extern __m256i _mm256_cmpgt_epi32(__m256i s1, __m256i s2);
extern __m256i _mm256_cmpgt_epi64(__m256i s1, __m256i s2);
Arguments
s1
integer destination vector used for the operation
s2
integer source vector used for the operation
Description
Performs a SIMD signed compare to determine which of the data elements [packed bytes, words, doublewords, or quadwords] in destination vector
s1
is greater than the corresponding element in the source vector
s2
.
For each pair of data elements in
s1
and
s2
, if the
s1
data element is greater than the corresponding element in
s2
, then the corresponding element in the destination vector is set to all 1s. If the
s1
data element is less than the corresponding data element in
s2
, then the corresponding data element in destination vector is set to all 0s.
If the data elements are equal, the destination vector is set to 0.
Returns
Destination vector with result of the compare greater-than operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804