Developer Guide and Reference

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_mm_fnmadd_pd, _mm256_fnmadd_pd

Multiply-adds negated packed double-precision floating-point values of three float64 vectors. The corresponding FMA instruction is
VFNMADD<XXX>PD
, where XXX could be 132, 213, or 231.

Syntax

For 128-bit vector
extern __m128d _mm_fnmadd_pd(__m128d a, __m128d b, __m128d c);
For 256-bit vector
extern __m256d _mm256_fnmadd_pd(__m256d a, __m256d b, __m256d c);
Arguments
a
float64 vector used for the operation
b
float64 vector also used for the operation
c
float64 vector also used for the operation
Description
Performs a set of SIMD negated multiply-add computation on packed double-precision floating-point values using three source vectors/operands,
a
,
b
, and
c
. Corresponding values in two operands,
a
and
b
, are multiplied and the negated infinite precision intermediate results are added to the values in the third operand,
c
, after which the final results are rounded to the nearest float64 values.
The compiler defaults to using the
VFNMADD213PD
instruction and uses the other forms
VFNMADD132PD
or
VFNMADD231PD
only if a low level optimization decides it as useful or necessary. For example, the compiler could change the default if it finds that another instruction form saves a register or eliminates a move.
Returns
Result of the negated multiply-add operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804