Developer Guide and Reference

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_mm_fnmadd_sd

Multiply-adds negated scalar double-precision floating-point values of three float64 vectors. The corresponding FMA instruction is
VFNMADD<XXX>SD
, where XXX could be 132, 213, or 231.

Syntax

extern __m128d _mm_fnmadd_sd(__m128d a, __m128d b, __m128d c);
Arguments
a
float64 vector used for the operation
b
float64 vector also used for the operation
c
float64 vector also used for the operation
Description
Performs a set of scalar SIMD negated multiply-add computation on scalar double-precision floating-point values in the low 64-bits of three source operands,
a
,
b
, and
c
. The float64 values in two operands,
a
and
b
, are multiplied and the negated infinite precision intermediate result obtained is added to the float64 value in the third operand,
c
. The final result is rounded to the nearest float64 value.
The compiler defaults to using the
VFNMADD213SD
instruction and uses the other forms
VFNMADD132SD
or
VFNMADD231SD
only if a low level optimization decides it as useful or necessary. For example, the compiler could change the default if it finds that another instruction form saves a register or eliminates a move.
Returns
Result of the negated multiply-add operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804