Developer Guide and Reference

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_mm_fnmsub_ss

Multiply-subtracts negated scalar single-precision floating-point values of three float32 vectors. The corresponding FMA instruction is
VFNMSUB<XXX>SS
, where XXX could be 132, 213, or 231.

Syntax

extern __m128 _mm_fnmsub_ss(__m128 a, __m128 b, __m128 c);
Arguments
a
float32 vector used for the operation
b
float32 vector also used for the operation
c
float32 vector also used for the operation
Description
Performs a set of scalar SIMD negated multiply-subtract computation on scalar single-precision floating-point values in the low 32-bits of three source operands,
a
,
b
, and
c
. The float32 values in two operands,
a
and
b
, are multiplied and the negated infinite precision intermediate result is obtained. From this negated intermediate result, the float32 value in the third operand,
c
, is subtracted. The final result is rounded to the nearest float32 value.
The compiler defaults to using the
VFNMSUB213SS
instruction and uses the other forms
VFNMSUB132SS
or
VFNMSUB231SS
only if a low level optimization decides it is useful or necessary. For example, the compiler could change the default if it finds that another instruction form saves a register or eliminates a move.
Returns
Result of the negated multiply-subtract operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804