Developer Guide and Reference



Gathers 2/4 quadword values from memory referenced by the given base address, dword indices and scale. The corresponding Intel® AVX2 instruction is


extern __m128i _mm_i32gather_epi64(__int64 const * base, __m128i vindex, const int scale);
extern __m256i _mm256_i32gather_epi64(__int64 const * base, __m128i vindex, const int scale);
the base address used to reference the loaded qword elements.
the vector of dword indices used to reference the loaded qword elements.
The compilation time literal constant, which is used as the vector indices scale to address the loaded elements. Possible values are one of the following: 1, 2, 4, 8.
The intrinsics load 2/4 quadword values from memory using the base address, dword indices, and 64-bit scale.
Below is the pseudo-code for the intrinsics:
result[63:0] = mem[base+vindex[31:0]*scale]; result[127:64] = mem[base+vindex[63:32]*scale];
result[63:0] = mem[base+vindex[31:0]*scale]; result[127:64] = mem[base+vindex[63:32]*scale]; result[191:128] = mem[base+vindex[95:64]*scale]; result[255:192] = mem[base+vindex[127:96]*scale];
A 128/256-bit vector with unconditionally gathered integer64 values.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804