Developer Guide and Reference


_mm_i64gather_ps, _mm256_i64gather_ps

Gathers 2/4 packed single-precision floating point values from memory referenced by the given base address, qword indices and scale. The corresponding Intel® AVX2 instruction is


extern __m128 _mm_mask_i64gather_ps(float const * base, __m128i vindex, const int scale);
extern __m128 _mm256_mask_i64gather_ps(float const * base, __m256i vindex, const int scale);
the base address used to reference the loaded FP elements.
the vector of qword indices used to reference the loaded FP elements.
The compilation time literal constant, which is used as the vector indices scale to address the loaded elements. Possible values are one of the following: 1, 2, 4, 8.
The intrinsics load 2/4 packed single-precision floating-point values from memory using qword indices and updates the destination operand. The intrinsic
also sets the upper 64-bits of the result to '
Below is the pseudo-code for the intrinsics:
result[31:0] = mem[base+vindex[63:0]*scale]; result[63:32] = mem[base+vindex[127:64]*scale]; result[127:64] = 0;
result[31:0] = mem[base+vindex[63:0]*scale]; result[63:32] = mem[base+vindex[127:64]*scale]; result[95:64] = mem[base+vindex[191:128]*scale]; result[127:96] = mem[base+vindex[255:192]*scale];
A 128/256-bit vector with unconditionally gathered single-precision FP values.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804