Developer Guide and Reference

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_mm_mask_i32gather_pd, _mm256_mask_i32gather_pd

Gathers 2/4 packed double-precision floating point values from memory referenced by the given base address, dword indices and scale, and using the given double-precision FP mask values. The corresponding Intel® AVX2 instruction is
VGATHERDPD
.

Syntax

extern __m128d _mm_mask_i32gather_pd(__m128d def_vals, double const * base, __m128i vindex __m128d vmask, const int scale);
extern __m256d _mm256_mask_i32gather_pd(__m256d def_vals, double const * base, __m128i vindex __m256d vmask, const int scale);
Arguments
def_vals
the vector of double-precision FP values copied to the destination when the corresponding element of the double-precision FP mask is '
0
'.
base
the base address used to reference the loaded FP elements.
vindex
the vector of dword indices used to reference the loaded FP elements.
vmask
the vector of FP elements used as a vector mask; only the most significant bit of each data element is used as a mask.
scale
The compilation time literal constant, which is used as the vector indices scale to address the loaded elements. Possible values are one of the following: 1, 2, 4, 8.
Description
The intrinsics conditionally load 2/4 packed double-precision floating-point values from memory using dword indices according to mask values and updates the destination operand.
Below is the pseudo-code for the intrinsics:
_mm_mask_i32gather_pd()
:
result[63:0] = (vmask[63]==1) ? (mem[base+vindex[31:0]*scale]) : (def_vals[63:0]); result[127:64] = (vmask[127]==1) ? (mem[base+vindex[63:32]*scale]) : (def_vals[127:64]);
_mm256_mask_i32gather_pd()
:
result[63:0] = (vmask[63]==1) ? (mem[base+vindex[31:0]*scale]) : (def_vals[63:0]); result[127:64] = (vmask[127]==1) ? (mem[base+vindex[63:32]*scale]) : (def_vals[127:64]); result[191:128] = (vmask[191]==1) ? (mem[base+vindex[95:64]*scale]) : (def_vals[191:128]); result[255:192] = (vmask[255]==1) ? (mem[base+vindex[127:96]*scale]) : (def_vals[255:192]);
Returns
A 128/256-bit vector with conditionally gathered double-precision FP values.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804