Developer Guide and Reference


Function Prototype and Macro Definitions

To use the prototypes and macro definitions shown in Group 1, include the
file as follows:
#include <immintrin.h>
Group 1: Function Prototypes:
unsigned int _xbegin(void);
void _xend(void); void _xabort(const unsigned int imm); unsigned char _xtest(void);
The following macro definitions are included in the
header file:
Group 1: Macro Definitions:
#define _XBEGIN_STARTED (~0u) #define _XABORT_EXPLICIT (1 << 0) #define _XABORT_RETRY (1 << 1) #define _XABORT_CONFLICT (1 << 2) #define _XABORT_CAPACITY (1 << 3) #define _XABORT_DEBUG (1 << 4) #define _XABORT_NESTED (1 << 5)
Group 2: Function Macros
The following function Macros are
included in
header file. If you want to use them, you need to define them in your applications.
For the HW with RTM support
#define __try_transaction(x) if ((x =_xbegin()) == _XBEGIN_STARTED) #define __try_else _xend() } else #define __transaction_abort(c) _xabort(c)
For the HW with no RTM support
#define __try_transaction(x) if (0) { #define __try_else } else #define __transaction_abort(c)
is an unsigned integer type local variable for programmers to access RTM transaction abort code and holds the return value of
is an unsigned integer compile-time constant value that is returned in the upper bits of
is executed.
A usage sample code of macros
foo() { // user macros int status; __try_transaction (status) { ,,, ,,, ,,, transaction code …. } __try_else { if (status & _XABORT_CONFLICT) { … code } } }
Pseudo-ASM code
foo() { or eax 0xffffffff xbegin L1 L1: mov status, eax cmp eax 0xffffffff jnz L2 transaction code // when abort happens, HW restarts from L1 xend jmp L3 L2: abort handler code L3: ret }
The compiler will convert the macros to the instruction sequence with a proper branching for speculative execution path and alternative execution path.
The above example is similar to the usage example, except
macros are used instead of RTM intrinsic functions.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804