Developer Guide and Reference

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Intel® Transactional Synchronization Extensions (Intel® TSX) Programming Considerations

Typical programmer-identified regions are expected to transactionally execute and commit successfully. However, Intel® Transactional Synchronization Extensions (Intel® TSX) does not provide any such guarantee. A transactional execution may abort for many reasons. To take full advantage of the transactional capabilities, programmers should take into account programming considerations to increase the probability of their transactional execution committing successfully.
This section discusses various events that may cause transactional aborts. The architecture ensures that updates performed within a transaction that subsequently aborts execution will not become visible: Only a committed transactional execution updates architectural state. Transactional aborts never cause functional failures and only affect performance.

Instruction Based Considerations

Programmers can use any instruction safely inside a transaction, Hardware Lock Elision (HLE) or Restricted Transactional Memory (RTM) and can use transactions at any privilege level. Some instructions will always abort the transactional execution and cause execution to seamlessly and safely transition to a non-transactional path.
Intel® TSX allows for most common instructions to be used inside transactions without causing aborts. The following operations inside a transaction do not typically cause an abort:
  • Operations on the instruction pointer register.
  • Operations on general purpose registers (
    GPR
    s).
  • Operations on the status flags (
    CF
    ,
    OF
    ,
    SF
    ,
    PF
    ,
    AF
    , and
    ZF
    ).
  • Operations on
    XMM
    and
    YMM
    registers.
  • Operations on the
    MXCSR
    register.
Programmers must be careful when intermixing Intel® Supplemental Streaming Extensions (Intel® SSE) and Intel® Advanced Vector Extensions (Intel® AVX) operations inside a transactional region. Intermixing Intel® SSE instructions accessing
XMM
registers and Intel® AVX instructions accessing
YMM
registers may cause transactions to abort.
Programmers may use
REP
/
REPNE
prefixed string operations inside transactions. However, long strings may cause aborts. Further, the use of
CLD
and
STD
instructions may cause aborts if they change the value of the
DF
flag. If
DF
is '
1
', the
STD
instruction will not cause an abort. Similarly, if
DF
is '
0
', the
CLD
instruction will not cause an abort.
Instructions not enumerated here as causing abort when used inside a transaction will typically not cause a transaction to abort (examples include but are not limited to
MFENCE
,
LFENCE
,
SFENCE
,
RDTSC
,
RDTSCP
, etc.).
The following instructions will abort transactional execution on any implementation:
  • XABORT
  • CPUID
  • PAUSE
In some implementations, the following instructions may always cause transactional aborts. These instructions are not expected to be commonly used inside typical transactional regions. Programmers must not rely on these instructions to force a transactional abort, since whether they cause transactional aborts is implementation dependent.
  • Operations on X87 and MMX™ architecture state. This includes all MMX™ and X87 instructions, including the
    FXRSTOR
    and
    FXSAVE
    instructions.
  • Update to non-status portion of EFLAGS:
    CLI
    ,
    STI
    ,
    POPFD
    ,
    POPFQ
    ,
    CLTS
    .
  • Instructions that update segment registers, debug registers and/or control registers:
    MOV
    to
    DS
    /
    ES
    /
    FS
    /
    GS
    /
    SS
    ,
    POP
    DS
    /
    ES
    /
    FS
    /
    GS
    /
    SS
    ,
    LDS
    ,
    LES
    ,
    LFS
    ,
    LGS
    ,
    LSS
    ,
    SWAPGS
    ,
    WRFSBASE
    ,
    WRGSBASE
    ,
    LGDT
    ,
    SGDT
    ,
    LIDT
    ,
    SIDT
    ,
    LLDT
    ,
    SLDT
    ,
    LTR
    ,
    STR
    ,
    Far CALL
    ,
    Far JMP
    ,
    Far RET
    ,
    IRET
    ,
    MOV
    to DRx,
    MOV
    to
    CR0
    /
    CR2
    /
    CR3
    /
    CR4
    /
    CR8
    , and
    LMSW
    .
  • Ring transitions:
    SYSENTER
    ,
    SYSCALL
    ,
    SYSEXIT
    , and
    SYSRET
    .
  • TLB and Cacheability control:
    CLFLUSH
    ,
    INVD
    ,
    WBINVD
    ,
    INVLPG
    ,
    INVPCID
    , and memory instructions with a non-temporal hint (
    MOVNTDQA
    ,
    MOVNTDQ
    ,
    MOVNTI
    ,
    MOVNTPD
    ,
    MOVNTPS
    , and
    MOVNTQ
    ).
  • Processor state save:
    XSAVE
    ,
    XSAVEOPT
    , and
    XRSTOR
    .
  • Interrupts:
    INTn
    ,
    INTO
    .
  • IO:
    IN
    ,
    INS
    ,
    REP INS
    ,
    OUT
    ,
    OUTS
    ,
    REP OUTS
    and their variants.
  • VMX:
    VMPTRLD
    ,
    VMPTRST
    ,
    VMCLEAR
    ,
    VMREAD
    ,
    VMWRITE
    ,
    VMCALL
    ,
    VMLAUNCH
    ,
    VMRESUME
    ,
    VMXOFF
    ,
    VMXON
    ,
    INVEPT
    , and
    INVVPID
    .
  • SMX:
    GETSEC
    ,
    UD2
    ,
    RSM
    ,
    RDMSR
    ,
    WRMSR
    ,
    HLT
    ,
    MONITOR
    ,
    MWAIT
    ,
    XSETBV
    ,
    VZEROUPPER
    ,