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_mm_srlv_epi32/64

Logical shift of word/doubleword elements in a 128-bit vector to right according variable values. The corresponding Intel® AVX2 instruction is
VPSRLVD
or
VPSRLVQ
.

Syntax

extern __m128i _mm_srlv_epi32(__m128i s1, __m128i s2);
extern __m128i _mm_srlv_epi64(__m128i s1, __m128i s2);
Arguments
s1
128-bit integer source vector used for the operation
s2
128-bit integer source vector providing variable values for shift operation
Description
Performs a logical shift of 32 or 64 bits (doublewords, or quadword) in the individual data elements in source vector
s1
to the right by the count value of corresponding data elements in the source vector
s2
. As the bits in the data elements are shifted right, the empty low-order bits are cleared (set to '
0
').
The count values are specified individually in each data element of the second source vector. If the unsigned integer value specified in the respective data element of the second source vector is greater than 31 (for a doubleword), or 63 (for a quadword), then the destination data element are set to '
0
'.
Returns
Result of the right-shift operation.