Developer Guide and Reference

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_mm256_sllv_epi32/64

Logical shift of doubleword/quadword elements to left according variable values. The corresponding Intel® AVX2 instruction is
VPSLLVD
or
VPSLLVQ
.

Syntax

extern __m256i _mm256_sllv_epi32(__m256i s1, __m256i s2);
extern __m256i _mm256_sllv_epi64(__m256i s1, __m256i s2);
Arguments
s1
integer source vector used for the operation
s2
integer source vector providing variable values for shift operation
Description
Performs a logical shift of 32 or 64 bits (doublewords, or quadword) in the individual data elements in source vector
s1
to the left by the count value of corresponding data elements in source vector
s2
. As the bits in the data elements are shifted left, the empty low-order bits are cleared (set to '
0
').
The count values are specified individually in each data element of the second source vector. If the unsigned integer value specified in the respective data element of the second source vector is greater than 31 (for a doubleword), or 63 (for a quadword), then the destination data elements are set to '
0
'.
Returns
Result of the left-shift operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804