Developer Guide and Reference

Contents

_mm256_srli_epi16/32/64

Logical shift of word/doubleword/quadword elements to right according to specified number. The corresponding Intel® AVX2 instruction is
VPSRLW
,
VPSRLD
, or
VPSRLQ
.

Syntax

extern __m256i _mm256_srli_epi16(__m256i s1, int count);
extern __m256i _mm256_srli_epi32(__m256i s1, int count);
extern __m256i _mm256_srli_epi64(__m256i s1, int count);
Arguments
s1
integer source vector used for the operation
count
8-bit immediate used for the operation
Description
Performs a logical shift of bits in the individual data elements (16-bit word, 32-bit doubleword, or 64-bit quadword) in source vector
s1
to the right by the number of bits specified in
count
. The empty low-order bytes are cleared (set to all '
0
'). If the value specified by
count
is greater than 15/31/63 (depending on the intrinsic being used), the destination vector is set to all '
0
'. The
count
argument is an 8-bit immediate.
Returns
Result of the right-shift operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804