Developer Guide and Reference



Performs packed move with zero-extend on 32-bit unsigned integers to 64-bit integers. The corresponding Intel® AVX2 instruction is


extern __m256i _mm256_cvtepu32_epi64(__m128i s1);
128-bit integer source vector used for the operation
Performs a packed move with zero-extend operation to convert 32-bit [doubleword] integers in the low bytes of the source vector,
, to 64-bit [quadword] integers and stored as packed signed quadword integers in the destination vector.
Result of the zero-extend operation.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804