Developer Guide and Reference

Contents

_mm256_cvtepu8_epi16/32/64

Performs packed move with zero-extend on 8-bit unsigned integers to 16/32/64-bit integers. The corresponding Intel® AVX2 instruction is
VPMOVZXBW
,
VPMOVZXBD
, or
VPMOVZXBQ
.

Syntax

extern __m256i _mm256_cvtepu8_epi16(__m128i s1);
extern __m256i _mm256_cvtepu8_epi32(__m128i s1);
extern __m256i _mm256_cvtepu8_epi64(__m128i s1);
Arguments
s1
128-bit integer source vector used for the operation
Description
Performs a packed move with zero-extend operation to convert 8-bit [byte] integers in the low bytes of the source vector,
s1
, to 16-bit [word], 32-bit [doubleword], or 64-bit [quadword] integers and stored as packed unsigned word/doubleword/quadword integers in the destination vector.
Returns
Result of the zero-extend operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804