Developer Guide and Reference

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_mm256_permutevar8x32_epi32

Permutes doubleword elements of the source vector into the destination vector. The corresponding Intel® AVX2 instruction is
VPERMD
.

Syntax

extern __m256i _mm256_permutevar8x32_epi32(__m256i val, __m256i offsets);
Arguments
val
the vector of 32-bit integer elements to be permuted
offsets
the vector of eight 3-bit offsets (specifying values in range [0 - 7]) for the permuted elements of 256-bit vector
Description
Use the offset values in each dword element of the vector
offsets
to select a dword element from the source vector
val
. The result element is copied to the corresponding element of destination vector. The intrinsic does NOT allow to copy the same element of the source vector to more than one element of the destination vector.
Below is the pseudo-code for the intrinsic:
RESULT[31:0] <- (VAL[255:0] >> (OFFSETS[2:0] * 32))[31:0]; RESULT[63:32] <- (VAL[255:0] >> (OFFSETS[34:32] * 32))[31:0]; RESULT[95:64] <- (VAL[255:0] >> (OFFSETS[66:64] * 32))[31:0]; RESULT[127:96] <- (VAL[255:0] >> (OFFSETS[98:96] * 32))[31:0]; RESULT[159:128] <- (VAL[255:0] >> (OFFSETS[130:128] * 32))[31:0]; RESULT[191:160] <- (VAL[255:0] >> (OFFSETS[162:160] * 32))[31:0]; RESULT[223:192] <- (VAL[255:0] >> (OFFSETS[194:192] * 32))[31:0]; RESULT[255:224] <- (VAL[255:0] >> (OFFSETS[226:224] * 32))[31:0];
Returns
Result of the permute operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804