Developer Guide and Reference

Contents

Intrinsics for Integer Subtraction Operations

The prototypes for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) intrinsics are located in the
zmmintrin.h
header file.
To use these intrinsics, include the
immintrin.h
file as follows:
#include <immintrin.h>
Intrinsic Name
Operation
Corresponding
Intel® AVX-512 Instruction
_mm512_sub_epi32
,
_mm512_maskz_sub_epi32
Subtracts int32 elements.
VPSUBD
_mm512_sub_epi64
,
_mm512_mask_sub_epi64
,
_mm512_maskz_sub_epi64
Subtracts int64 elements.
VPSUBQ
variable
definition
k
writemask used as a selector
a
first source vector element
b
second source vector element
src
source element to use based on writemask result
_mm512_sub_epi32
extern __m512i __cdecl _mm512_sub_epi32(__m512i a, __m512i b);
Subtracts packed 32-bit integers in
b
from packed 32-bit integers in
a
, and stores the result.
_mm512_maskz_sub_epi32
extern __m512i __cdecl _mm512_maskz_sub_epi32(__mmask16 k, __m512i a, __m512i b);
Subtracts packed 32-bit integers in
b
from packed 32-bit integers in
a
, and stores the result using zeromask
k
(elements are zeroed out when the corresponding mask bit is not set).
_mm512_sub_epi64
extern __m512i __cdecl _mm512_sub_epi64(__m512i a, __m512i b);
Subtracts packed 64-bit integers in
b
from packed 64-bit integers in
a
, and stores the result.
_mm512_mask_sub_epi64
extern __m512i __cdecl _mm512_mask_sub_epi64(__m512i src, __mmask8 k, __m512i a, __m512i b);
Subtracts packed 64-bit integers in
b
from packed 64-bit integers in
a
, and stores the result using writemask
k
(elements are copied from
src
when the corresponding mask bit is not set).
_mm512_maskz_sub_epi64
extern __m512i __cdecl _mm512_maskz_sub_epi64(__mmask8 k, __m512i a, __m512i b);
Subtracts packed 64-bit integers in
b
from packed 64-bit integers in
a
, and stores the result using zeromask
k
(elements are zeroed out when the corresponding mask bit is not set).

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804