Developer Guide and Reference

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Details of Intel® Advanced Vector Extensions Intrinsics

Intel® Advanced Vector Extensions (Intel® AVX) intrinsics map directly to Intel® AVX instructions and other enhanced 128-bit single-instruction multiple data processing (SIMD) instructions. Intel® AVX instructions are architecturally similar to extensions of the existing Intel® 64 architecture-based vector streaming SIMD portions of Intel® Streaming SIMD Extensions (Intel® SSE) instructions, and double-precision floating-point portions of Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions. However, Intel® AVX introduces the following architectural enhancements:
  • Support for 256-bit wide vectors and SIMD register set.
  • Instruction syntax support three and four operand syntax, to improve instruction programming flexibility and efficiency for new instruction extensions.
  • Enhancement of legacy 128-bit SIMD instruction extensions to support three-operand syntax and to simplify compiler vectorization of high-level language expressions.
  • Instruction encoding format using a new prefix (referred to as VEX) to provide compact, efficient encoding for three-operand syntax, vector lengths, compaction of legacy SIMD prefixes and REX functionality.
  • Intel® AVX data types allow packing of up to 32 elements in a register if bytes are used. The number of elements depends upon the element type: eight single-precision floating point types or four double-precision floating point types.

Intel® Advanced Vector Extensions Registers

Intel® AVX adds 16 registers (
YMM0-YMM15
), each 256 bits wide, aliased onto the 16 SIMD (
XMM0-XMM15
) registers. The Intel® AVX new instructions operate on the
YMM
registers. Intel® AVX extends certain existing instructions to operate on the
YMM
registers, defining a new way of encoding up to three sources and one destination in a single instruction.
Because each of these registers can hold more than one data element, the processor can process more than one data element simultaneously. This processing capability is also known as single-instruction multiple data processing (SIMD).
For each computational and data manipulation instruction in the new extension sets, there is a corresponding C intrinsic that implements that instruction directly. This frees you from managing registers and assembly programming. Further, the compiler optimizes the instruction scheduling so that your executable runs faster.

Intel® Advanced Vector Extensions Types

The Intel® AVX intrinsic functions use three new C data types as operands, representing the new registers used as operands to the intrinsic functions. These are
__m256
,
__m256d
, and
__m256i
data types.
The
__m256
data type is used to represent the contents of the extended SSE register, the
YMM
register, used by the Intel® AVX intrinsics. The
__m256
data type can hold eight 32-bit floating-point values.
The