Developer Guide and Reference

Contents

_mm256_addsub_pd

Adds odd float64 elements and subtracts even float64 elements of vectors. The corresponding Intel® AVX instruction is
VADDSUBPD
.

Syntax

extern __m256d _mm256_addsub_pd(__m256d m1, __m256d m2);
Arguments
m1
float64 vector used for the operation
m2
float64 vector also used for the operation
Description
Performs a SIMD addition of the odd packed double-precision floating-point elements (float64 elements) from the first source vector
m1
to the odd float64 elements of the second source vector
m2
.
Simultaneously, the intrinsic performs subtraction of the even double-precision floating-point elements of the second source vector
m2
from the even float64 elements of the first source vector
m1
.
Returns
Result of the operation is stored in the result vector, which is returned by the intrinsic.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804