Developer Guide and Reference

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_mm256_blendv_ps

Performs conditional blend/merge of float32 vectors. The corresponding Intel® AVX instruction is
VBLENDVPS
.

Syntax

extern __m256 _mm256_blendv_ps(__m256 m1, __m256 m2, __m256 mask);
Arguments
m1
float32 vector used for the operation
m2
float32 vector also used for the operation
mask
float32 vector with the mask for the operation; defined such that the “1” in the most significant bits of an element indicate that corresponding elements of the second source vector are copied into the result, while “0” bits indicate that corresponding elements of the first source vector are copied into the result
Description
Performs a conditional merge of eight packed single-precision floating point elements (float32 elements) of two vectors according to the most significant bits of the
mask
parameter.
The
mask
parameter defines a mask for the operation. The most significant bit of the corresponding single-precision floating-point elements in the
mask
determines whether the corresponding single-precision floating-point element in the resulting vector is copied from the second source or first source.
If the bit in the
mask
is “1” then the corresponding element of the second source vector is copied into the resulting vector. If the bit is “0” then the corresponding element of the first source vector is copied into the resulting vector. Thus a merging/blending of the elements of the two source vectors occurs when this intrinsic is used.
Returns
Result of the blend operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804