Developer Guide and Reference

Contents

_mm256_maskstore_pd, _mm_maskstore_pd

Stores packed double-precision floating point values according to mask values. The corresponding Intel® AVX instruction is
VMASKMOVPD
.

Syntax

extern void _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
extern void _mm_maskstore_pd(double *a, __m128i mask, __m128d b);
Arguments
*a
pointer to a 256/128-bit memory location that can hold constant double-precision floating point (float64) values
mask
integer value calculated based on the most-significant-bit of each quadword of a mask register
b
a 256/128-bit float64 vector
Description
Performs a store operation by moving packed double-precision floating point (float64) values from a vector,
b
, to a 256/128-bit memory location, pointed to by
a
, using a
mask
.
The
mask
is calculated from the most significant bit of each qword of the
mask
register. If any of the bits of the mask are set to zero, the corresponding value from the float64 vector is not loaded, and the corresponding field of the destination memory location is left unchanged.
Stores are atomic. Faults do not occur for memory locations for which all corresponding mask bits are set to zero.
Returns
Nothing.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804