Developer Guide and Reference

Contents

_mm256_round_ps

Rounds off single-precision floating point values to nearest upper/lower integer depending on rounding mode. The corresponding Intel® AVX instruction is
VROUNDPS
.

Syntax

extern __m256 _mm256_round_ps(__m256 a, int iRoundMode );
Arguments
a
float32 vector
iRoundMode
A hexadecimal value dependent on rounding mode:
  • For rounding off to upper integer, the value is
    0x0A
  • For rounding off to lower integer, the value is
    0x09
Description
Rounds off the elements of a float32 vector
a
to the nearest upper/lower integer value. Two shortcuts, in the form of
#defines
, are used to achieve these two separate operations:
#define _mm256_ceil_ps(a) _mm256_round_ps((a), 0x0A) #define _mm256_floor_ps(a) _mm256_round_ps((a), 0x09)
These
#defines
tells the preprocessor to replace all instances of
_mm256_ceil_ps(a
) with
_mm256_round_ps((a), 0x0A)
and all instances of
_mm256_floor_ps(a)
with
_mm256_round_ps((a), 0x09)
.
For example, if you write the following:
__m256 a, b; a = _mm256_ceil_ps(b);
the preprocessor will modify it to:
a = _mm256_round_ps(b, 0x0a);
The Precision Floating Point Exception is signaled according to the (immediate operand)
iRoundMode
value.
Returns
Result of the rounding off operation as a vector with single-precision floating point values.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804