Developer Guide and Reference

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_mm256_testz_pd, _mm_testz_pd

Performs a packed bit test of two float64 256-bit or 128-bit vectors to set the ZF flag. The corresponding Intel® AVX instruction is
VTESTPD
.

Syntax

extern int _mm256_testz_pd(__m256d s1, __m256d s2);
extern int _mm_testz_pd(__m128d s1, __m128d s2);
Arguments
s1
first float64 source vector
s2
second float64 source vector
Description
Compute the bitwise AND of the two vectors s1 and s2, representing double-precision (64-bit) floating-point elements, producing an intermediate value, and set ZF to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ZF to 0. Compute the bitwise AND NOT of s1 and s2, producing an intermediate value, and set CF to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set CF to 0. Return the ZF value.
Intel® Advanced Vector Extensions (Intel® AVX) instructions include a full compliment of 128-bit SIMD instructions. Such Intel® AVX instructions, with vector length of 128-bits, zeroes the upper 128 bits of the
YMM
register. The lower 128 bits of the
YMM
register is aliased to the corresponding SIMD
XMM
register.
Returns
Non-zero if ZF flag is set
Zero if the ZF flag is not set