Developer Guide and Reference

Contents

Load Intrinsics

Intel® Streaming SIMD Extensions 2 (Intel® SSE2) intrinsics for integer load operations are listed in this topic. The prototypes for Intel® SSE2 intrinsics are in the
emmintrin.h
header file.
To use these intrinsics, include the
immintrin.h
file as follows:
#include <immintrin.h>
The results of each intrinsic operation are placed in registers. The information about what is placed in each register appears in the tables below, in the detailed explanation of each intrinsic.
R
,
R0
, and
R1
represent the registers in which results are placed.
Intrinsic Name
Operation
Corresponding Intel® SSE2 Instruction
_mm_load_si128
Load
MOVDQA
_mm_loadu_si128
Load
MOVDQU
_mm_loadl_epi64
Load and zero
MOVQ

_mm_load_si128

__m128i _mm_load_si128(__m128i const*p);
Loads 128-bit value. Address
p
must be 16-byte aligned.
R
*p

_mm_loadu_si128

__m128i _mm_loadu_si128(__m128i const*p);
Loads 128-bit value. Address
p
not need be 16-byte aligned.
R
*p

_mm_loadl_epi64

__m128i _mm_loadl_epi64(__m128i const*p);
Load the lower 64 bits of the value pointed to by
p
into the lower 64 bits of the result, zeroing the upper 64 bits of the result.
R0
R1
*p[63:0]
0x0

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804