Developer Guide and Reference

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Cacheability Support Intrinsic

The prototype for this Intel® Streaming SIMD Extensions (Intel® SSE4) intrinsic is in the
smmintrin.h
file.
To use this intrinsic, include the
immintrin.h
file as follows:
#include <immintrin.h>

_mm_stream_load_si128

extern __m128i _mm_stream_load_si128(__m128i* v1);
Loads
__m128
data from a 16-byte aligned address,
v1
, to the destination operand,
m128i
without polluting the caches.
Corresponding instruction:
MOVNTDQA

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804