Developer Guide and Reference

Contents

Register Insertion/Extraction Intrinsics

These Intel® Streaming SIMD Extensions (Intel® SSE4) intrinsics enable data insertion and extraction between general purpose registers and
XMM
registers. The prototypes for these intrinsics are in the
smmintrin.h
file.
To use these intrinsics, include the
immintrin.h
file as follows:
#include <immintrin.h>
Intrinsics marked with * are implemented only on Intel® 64 architectures. The rest of the intrinsics are implemented on both IA-32 and Intel® 64 architectures.
Intrinsic Syntax
Operation
Corresponding
Intel® SSE4 Instruction
__m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx)
Insert single precision float into packed single precision array element selected by index.
INSERTPS
int _mm_extract_ps(__m128 src, const int ndx)
Extract single precision float from packed single precision array element selected by index.
EXTRACTPS
__m128i _mm_insert_epi8(__m128i s1, int s2, const int ndx)
Insert integer byte into packed integer array element selected by index.
PINSRB
int _mm_extract_epi8(__m128i src, const int ndx)
Extract integer byte from packed integer array element selected by index.
PEXTRB
int _mm_extract_epi16(__m128i src, int ndx)
Extract integer word from packed integer array element selected by index.
PEXTRW
__m128i _mm_insert_epi32(__m128i s1, int s2, const int ndx)
Insert integer doubleword into packed integer array element selected by index.
PINSRD
int _mm_extract_epi32(__m128i src, const int ndx)
Extract integer doubleword from packed integer array element selected by index.
PEXTRD
__m128i _mm_insert_epi64(__m128i s2, int s, const int ndx)*
Insert integer quadword into packed integer array element selected by index. Use only on Intel® 64 architectures.
PINSRQ
__int64 _mm_extract_epi64(__m128i src, const int ndx)*
Extract integer quad word from packed integer array element selected by index. Use only on Intel® 64 architectures.
PEXTRQ

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804