Developer Guide and Reference

Contents

Test Intrinsics

These Intel® Streaming SIMD Extensions (Intel® SSE4) intrinsics perform packed integer 128-bit comparisons. The prototypes for these intrinsics are in the
smmintrin.h
file.
To use these intrinsics, include the
immintrin.h
file as follows:
#include <immintrin.h>
Intrinsic Name
Operation
Corresponding
Intel® SSE4 Instruction
_mm_testz_si128
Checks for all zeros in specified bits of a 128-bit value
PTEST
_mm_testc_si128
Checks for all ones in specified bits of a 128-bit value
PTEST
_mm_testnzc_si128
Checks for at least one '0' and at least one '1' in the specified bits of a 128-bit value
PTEST

_mm_testz_si128

int _mm_testz_si128(__m128i s1, __m128i s2);
Returns '
1
' if the bitwise AND operation on
s1
and
s2
results in all zeros, else returns '
0
'. That is,
_mm_testz_si128 := ( (s1 & s2) == 0 ? 1 : 0 )
This intrinsic checks if the
ZF
flag equals '
1
' as a result of the instruction
PTEST
s1
,
s2
. For example, it allows you to check if all set bits in
s2
(mask) are zeros in
s1
.
Corresponding instruction:
PTEST

_mm_testc_si128

int _mm_testc_si128(__m128i s1, __m128i s2);
Returns '
1
' if the bitwise AND operation on
s2
and logical NOT
s1
results in all zeros, else returns '
0
'. That is,
_mm_testc_si128 := ( (~s1 & s2) == 0 ? 1 : 0 )
This intrinsic checks if the
CF
flag equals '
1
' as a result of the instruction
PTEST
s1
,
s2
. For example it allows you to check if all set bits in
s2
(mask) are also set in
s1
.
Corresponding instruction:
PTEST

_mm_testnzc_si128

int _mm_testnzc_si128(__m128i s1, __m128i s2);
Returns '
1
' if the following conditions are true: bitwise operation of
s1
AND
s2
does not equal all zeros and bitwise operation of NOT
s1
AND
s2
does not equal all zeros, otherwise returns '
0
'. That is,
_mm_testnzc_si128 := ( ( (s1 & s2) != 0 && (~s1 & s2) != 0 ) ? 1 : 0 )
This intrinsic checks if both the
CF
and
ZF
flags are not '
1
' as a result of the instruction
PTEST
s1
,
s2
. For example, it allows you to check that the result has both zeros and ones in
s1
on positions specified as set bits in
s2
(mask).
Corresponding instruction:
PTEST

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804