Developer Guide and Reference

Contents

Overview: Intrinsics for 4th Generation Intel® Core™ Processor Instruction Extensions

The 4th Generation Intel® Core™ Processor Instruction Extensions intrinsics are assembly-coded functions that call on 4th Generation Intel® Core™ Processor Instructions that include scalar instructions targeted for Intel® 64 architecture processors in process technology smaller than 32nm.
To use these intrinsics, include the
immintrin.h
file as follows:
#include <immintrin.h>
These intrinsics map directly to the instructions defined in the "CHAPTER 9. ADDITIONAL NEW INSTRUCTIONS" section of
"Intel® Advanced Vector Extensions Programming Reference"
( http://software.intel.com/en-us/avx/ ).

Functional Overview

The 4th Generation Intel® Core™ Processor Instruction Extensions include:
  • Four intrinsics that map to two hardware instructions
    ADOX
    and
    ADCX
    performing 32-bit or 64-bit arithmetic operations with flags.
  • One intrinsic that maps to the hardware instruction,
    PREFETCHW
    . This intrinsic allows data to be to prefetched into the cache in anticipation of a write. This intrinsic can be found in the Cacheability Support Intrinsics section.
  • Three intrinsics that map to the hardware instruction
    RDSEED
    . The intrinsics generate random numbers of 16/32/64 bit wide random integers.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804